Synchronous dynamic random access memory (SDRAM) allows commands to arrive at the memory at defined intervals. The intervals are typically defined by a clock signal. For example, an interval may be one or more clock cycles or a fraction of a clock cycle. The commands may arrive at a specific time in the clock cycle during the interval, for example, on rising and/or falling clock edges. Similarly, output data provided by the memory may be driven to a data bus at defined intervals and/or at a specific time in the clock cycle. The synchronization of command inputs and data outputs with a clock signal may improve predictability of event timing and reliable operation of the memory.
Typically, SDRAM receives an external clock signal (e.g. “the system clock signal”). The SDRAM may include an internal clock circuit that produces an internal clock signal based on the external clock signal. The internal clock signal may be used to synchronize internal SDRAM operations with the external clock signal. For example, the internal clock signal may adjust when output data and/or an output data strobe is provided on the data bus from the memory so that the output data is provided more closely to a clock edge of the external clock signal. As a result, the output data from the memory may be more reliably latched.
A delay-lock loop (DLL) or a phase-lock loop (PLL) may be used in the internal clock circuit to generate the internal clock signal from the external clock signal. A DLL adds an appropriate delay to the external signal to produce the internal clock signal to synchronize memory input/output (I/O) operations. A PLL phase-matches the external clock signal and the internal clock signal.
In some applications, it may be desirable to have a high frequency internal clock signal. This may allow certain memory operations to be performed at a higher rate. However, increasing the internal clock signal may require increasing the external clock signal, which may be detrimental to operations performed by the host. Increasing the frequency of the internal clock signal may increase the memory's power requirements. For example, distributing the clock signal throughout the memory via widespread high-speed clock trees requires more power as the clock signal frequency increases. Increased power consumption may be undesirable in some applications.